An integrated circuit (IC) is an electronic circuit that is formed in or on a die, such as crystalline silicon, and is packaged as a discrete electrical component/unit.
Various methods of testing complex integrated circuits have been developed. A conventional method of testing integrated circuits involves sending a series of test vectors (electrical signals) to the input terminals of the device under test (DUT) and comparing its response (output signals) to a previously generated data set. For example, a typical integrated circuit tester, such as the Schlumberger model number ITS9000KX, sends a particular electrical digital test pattern to the DUT. The DUT responds to these incoming signals and sends output signals back to the tester. The tester then compares these output signals to the expected response, and a test failure is flagged if there is a mismatch.
As integrated circuits become more complex, the generation of a complete set of test vectors and responses utilizing the above-described test method has become almost impossible. One solution to this test problem involves the introduction of on-chip test methods, such as scan chains. A scan chain, or shift register, is an on-chip circuit used to input and capture test signals to and from the IC. In particular, the scan chain serially loads data to a section of the IC and sets the input nodes of this section to a known state. The responses or outputs from the section are later latched into the scan chain, further facilitating the testing process. As such, the static logic function of separate sections of the IC can be confirmed or tested in this manner.
Although scan chains have generally improved and facilitated IC testing at low speeds, scan chain capabilities may not be compatible with testing the full speed internal dynamic behavior of all ICs. For example, circuits including timing components, such as high frequency clock generators, will greatly complicate the accurate loading and latching of internal node data “on the fly” via the scan chain. Because of this, the on-chip time relationship between voltage transitions on two or more nodes may not be accurately represented from the data obtained using existing scan chain methods.
A proposal to solve this problem for integrated circuits and related devices is disclosed in co-pending U.S. patent application, entitled “On-Chip Optically Triggered Latch for IC Time Measurements,” Kenneth R. Wilsher, filed Sep. 28, 2000, Ser. No. 09/675,090, now U.S. Pat. No. 6,501,288, (the subject matter of which is incorporated herein by reference). In that disclosure, it is shown that a light pulse can be used as a trigger pulse to an on-chip data latch. By design, selected nodes of the IC are connected to the data input terminals of the optically triggered latches. The light pulse provides a very accurate timing signal that can be directed to any light sensitive latch in any part of the IC. The latched state is then read out via a scan chain. Since the light pulse can be directed at light sensitive elements at separate locations on the IC, it is possible, by repeating the test, to obtain test data on these widely separate selected nodes with confidence that the recorded time relationships are a very accurate representation of the actual on-chip electrical activity. Therefore, accurate clock path and logic path timing measurements can be made using this test method.
The optical system to deliver the light pulse as described above is a laser scanning microscope (LSM). An example of such a microscope is the LSM supplied by Checkpoint Technologies. FIG. 1 illustrates a cross-sectional side view of relevant portions of an exemplary optical system 10 and DUT 12. The DUT 12 includes a semiconductor device 14 that is electrically and mechanically coupled to a multilayer substrate 16 by ball-bonds 18. Electrical signal and power connections are made between multilayer substrate 16 and the test system multi-layer printed circuit board 15 via compliant connections 17. The device 14 includes a semiconductor substrate 20 (or die) having one or more circuit elements (or targets 22) formed within the substrate 20. In general, the optical system 10 consists of a microscope 24 having one or more lenses 26 used to focus a beam of light 28 onto the light sensitive element/target 22.
In order to be able to observe the various targets 22 of the integrated circuit and direct the light pulse 28 to the various light sensitive elements 22 on the die, the original cover plate or heat sink of the DUT 12 must be removed, as it would completely block the optical beam. Some heat sinking however may still be necessary because the DUT 12, which is operating during the testing, otherwise could overheat.
An alternative heat sinking arrangement 30 can be provided whereby a heat sink is prepared so as to expose only sections of the backside of the semiconductor substrate 20 above the locations of the light sensitive targets. Preferably, the exposed substrate 20 of the DUT 12 is polished and anti-reflection coated.
During use, a light beam or pulse 28 passes through one or more lenses 26, into the silicon substrate 20, and is brought into focus at the target 22. The target 22 is generally a diffusion region that has very small extension, typically less than a micrometer, in the vertical direction. To obtain good resolution, the lens 26 has high numerical aperture and is positioned very near the surface of the silicon substrate 20 and, thereby, the target 22, leaving room only for a thin heat sink 30. As such, this arrangement allows optical probing of the light sensitive elements 22 of the DUT 12 by focussing the light pulse through holes located in the modified heat sink structure 30 corresponding to specific test sites on the die.
The above-described method of using a light pulse to test integrated circuits offers many advantages over current methods, including improved ease of operation and timing accuracy. However, since microscope 24 can only direct the beam to one light sensitive element at a time, it would be useful to have a low cost system and/or method whereby different targets on the DUT can be probed simultaneously or in rapid succession without requiring re-alignment of the microscope. It would also be useful to have an optical test system and method that allows the DUT to be probed with a good heat sink attached. Elimination of the LSM and complex heat sinking would allow optical probing while the DUT is operating in its normal system environment, such as a computer board, rather than in a special test arrangement.